The present invention relates to a technology for laying out semiconductor devices and more specifically to a technology effectively applicable to the disposition of pads for efficiently laying out a large capacity memory, such as a DRAM and a synchronous DRAM (SDRAM).
The technological problem in DRAMs and SDRAMs which the inventor has examined is that the number of bits tends to be multiplied from ×4 to ×16 and ×32 and the number of pads tends to be also increased. For instance, while the number of input/output pins in a 64 M-bit DRAM (×4, ×8 and ×16 have been realized by a bonding option) is 54 in the package, the DRAM requires about 70 pads as internal pads, including normal signal pads, such as address, clock and data signal pads, power source pads, experimental pads and bonding option pads (for switching ×4 through ×16 and for switching the number of banks). It also requires predetermined pad dimensions and spaces therebetween, and it has become difficult to array the pads in a row for the LOC method gradually in the shrink generation. Even if they can be arrayed in a row, it has become difficult to assure large channel and power source bus regions between them in their gap.
A step-down system or a voltage regulator is often adopted in recent high-integrated memories, so that a variety of power source lines are required within a chip.
They include VDD, VSS, VDDQ and VSSQ lines as the external power source lines, and VPERI (for a peripheral circuit), VDL (for a memory array), VPP (for a boost word driver) and VBB (for biasing an array substrate) lines as the internal power source lines. Still more, the power source lines may be divided into those for the memory arrays (VDDA, VSSA), those for the general peripheral circuits (VDD, VSS) and those for the input circuits (VDDI, VSSI) as measures to counter noises. Thus, it has become difficult to dispose the pads adequately due to the increase in the number of the pads owing to the multiplication of bits and the variety of power source lines which have come to be required due to the high integration in memories, such as the DRAM and SDRAM.
It is noted that an example of the technology related to large capacity memories, such as the DRAM and SDRAM, is described in “Advanced Electronics I-9, Super LSI Memory” published by Baifukan Co., Ltd. on Nov. 5, 1994.
Japanese Patent Laid-open No. 116865/1991 has disclosed a semiconductor memory device in which direct peripheral circuits are disposed in a region between two memory cell arrays along the respective memory cell arrays, in-direct peripheral circuits are disposed in a region between the direct peripheral circuits along one direct peripheral circuit, external terminals are disposed in the region between the direct peripheral circuits along the other direct peripheral circuit and a substrate voltage generating circuit is disposed in a region between the indirect peripheral circuit and the external terminal.
U.S. Pat. No. 5,579,256 (corresponding to Japanese Patent Laid-Open No. 134568/1998) has disclosed a semiconductor device in which bonding pads, a voltage converter, a substrate voltage generating circuit and others are disposed at the center part of the chip.
U.S. Pat. No. 5,473,198 (corresponding to Japanese Patent Laid-open No. 350052/1994) has disclosed a semiconductor device in which axially symmetrical data input/output pads are disposed in two rows in parallel at the center part of the semiconductor chip.
U.S. Pat. No. 5,640,362 (corresponding to Japanese Patent Laid-open No. 128973/1997) has disclosed a synchronous semiconductor memory device having a plurality of data input/output pad groups 20 positioned at the right and left sides based on the center of a semiconductor chip 100, disposed in a row horizontally between upper and lower memory bank arrays 0 through 7 and having the same number with the memory array banks 0 through 7 to input/output information to/from the memory array banks 0 through 7.
U.S. Pat. No. 5,619,472 (corresponding to Japanese Patent Laid-Open No. 139287/1996) has disclosed a center pad disposed type semiconductor memory device in which an IO pad array, i.e., a first pad array, is disposed between a core block 1 and a core block 2 and an address pad array, i.e., a second pad array, is disposed between a core block 3 and a core block 4.
U.S. Pat. No. 5,627,792 (corresponding to Japanese Patent Laid-Open No. 125143/1996) has disclosed a semiconductor memory device in which respective pins (power source pins, ground pins, data input/output pins, control system signal pins, address system signal pins) of a lead frame are connected to bonding pad groups disposed along a center line in the center part of a semiconductor substrate by bonding wires 55.